The use of commercial-off-the-shelf (COTS) servers has been one of the pillars of the Open RAN revolution – delivering lower costs, vendor interoperability and, more recently, energy management.
But the performance of today’s Intel architecture COTS servers for Open RAN didn’t happen by chance. Intel and Rakuten Symphony have been working together since the earliest days of the industry when the technology was referred to as “extensible radio access network” (xRAN).
To explore the impact and future of this long partnership, I hosted a conversation between Raghunath Hariharan, CTO at Rakuten Symphony and Udayan Mukherjee, Senior Fellow and the Chief Architect of Wireless Product at Intel Network and Edge Group.
Here are the highlights of the conversation. I encourage you to watch the video of the conversation for the full context.
We started the discussion by taking a look at the history of the relationship which started in late 2016 with joint discussions on migrating the RAN from proprietary hardware that used expensive digital signal processors (DSPs) for layer 1 and layer 2 processing, to a more versatile processor-based platform.
“And with each generation of the Intel Xeon processors, we have evolved in adding more features, more functionality, more optimizations and better utilization of the CPU,” said Hariharan.
In fact, 4th Gen Intel Xeon Scalable processors with Intel vRAN Boost can be considered the crowning achievement of the collaboration to date. As Udayan put it: “This processor is tailor made for virtual RAN.”
One example of these innovations that make the latest Intel processor family ideal for vRAN can be seen in the evolution of the lookaside acceleration engine required for DU performance. This accelerator offloads compute-heavy channel coding processing from the main CPU. In the first iteration, the companies partnered on an FPGA design, then they used Intel’s structured ASIC innovation called Intel eASIC and now this accelerator is integrated into the Intel vRAN Boost that is part of the 4th Gen Intel Xeon Scalable processor. With each step in this evolution, the companies are enhancing performance and integration.
Much of the work between the companies focuses on the distributed unit (DU). Using Intel technology, Rakuten Symphony has designed the Symware™ next generation distributed unit platform, evolving from the Symware 1.0 server to Symware 2.0, a next-generation reference design for DU applications. “Symware 2.0 is a product design of a lot of years of innovation working together with Intel to solve a very complicated problem,” Hariharan said.
Symware 2.0 design makes full use of the 4th Gen Intel Xeon Scalable processors with Intel vRAN Boost to deliver the performance needed but with a significant reduction in power, size and cost.
Improving power management in a vRAN network starts with silicon. Intel plays a crucial role in supporting multiple power management states that can reduce the frequency on each compute core in a CPU when max performance is not needed due to reduced or off-peak network traffic levels. Additionally, emerging power management tools, such as advanced telemetry, provide valuable insights into CPU and system resource utilization.
Both executives emphasized the strength of their collaborative relationship, actively looking ahead at technology and standards developments. The companies are looking at new vRAN features for the next generation Intel Xeon-D Processor to bring more integrated functionality and instruction sets to boost the performance of this processor.
The companies are actively working on the next 5G standard - Release 18 from the 3GPP - to see what new functions will be part of the standards. In the marketplace, the Rakuten Symphony and Intel have teamed up for vRAN trials at major operators that are happening around the world.
Both companies also share the belief that the next generation of wireless networks will be driven by automation because networks will require a much larger number of small cell base stations making the complexity manageable only with automation.
The collective effort aims to ensure that advancements in CPU and system design directly benefit COTS platforms, enabling them to provide the required performance and feature set to stay ahead of evolving network demands and changes.
For a deeper dive into our conversation, we encourage you to explore the full session and discover more about our shared vision for the future.